The fabrication of various solid state devices requires the use of planar substrates, or semiconductor wafers, on which integrated circuits are fabricated. The final number, or yield, of functional integrated circuits on a wafer at the end of the IC fabrication process is of utmost importance to semiconductor manufacturers, and increasing the yield of circuits on the wafer is the main goal of semiconductor fabrication. After packaging, the circuits on the wafers are tested, wherein non-functional dies are marked using an inking process and the functional dies on the wafer are separated and sold. IC fabricators increase the yield of dies on a wafer by exploiting economies of scale. Over 1000 dies may be formed on a single wafer which measures from six to twelve inches in diameter.
Various processing steps are used to fabricate integrated circuits on a semiconductor wafer. These steps include deposition of a conducting layer on the silicon wafer substrate; formation of a photoresist or other mask such as titanium oxide or silicon oxide, in the form of the desired metal interconnection pattern, using standard lithographic or photolithographic techniques; subjecting the wafer substrate to a dry etching process to remove the conducting layer from the areas not covered by the mask, thereby etching the conducting layer in the form of the masked pattern on the substrate; removing or stripping the mask layer from the substrate typically using reactive plasma and chlorine gas, thereby exposing the top surface of the conductive interconnect layer; and cooling and drying the wafer substrate by applying water and nitrogen gas to the wafer substrate.
The numerous processing steps outlined above are used to cumulatively apply multiple electrically conductive and insulative layers on the wafer and pattern the layers to form the circuits. The final yield of functional circuits on the wafer depends on proper application of each layer during the process steps. Proper application of those layers depends, in turn, on coating the material in a uniform spread over the surface of the wafer in an economical and efficient manner.
The photolithography step of semiconductor production is a complex process which can generally be divided into an eight-step procedure including vapor prime, in which the surface of the wafer substrate is cleaned, dehydrated and primed to promote adhesion between the photoresist material and the substrate surface; spin coating, in which a quantity of liquid photoresist is applied to the substrate either before or during rotation of the substrate; soft bake, in which most of the solvent in the resist is driven off by heating the substrate; alignment and exposure, in which a mask or reticle corresponding to the desired circuit pattern is aligned to the correct location on the substrate and light energy is applied through the mask or reticle onto the photoresist to define circuit patterns which will be etched in a subsequent processing step to define the circuits on the substrate; post-exposure bake; develop, in which the soluble areas of photoresist are dissolved by liquid developer, leaving visible islands and windows corresponding to the circuit pattern on the substrate surface; hard bake, in which the remaining photoresist solvent is evaporated from the substrate; and develop inspect, in which an inspection is carried out in order to verify the quality of the resist pattern.
Resists which are determined by development inspection to be defective can be removed through resist stripping for re-processing of the substrate. Those resists which are determined not to be defective are subjected to etching, in which those areas of a conductive layer on the substrate not covered by the photoresist are etched and those areas covered by the photoresist are protected, leaving the circuit pattern in the conductive layer on the substrate. Alternatively, the photoresist may cover an electrically-insulating dielectric layer, in which case the areas of the dielectric layer not covered by the photoresist are etched and those areas covered by the photoresist are protected, leaving the circuit pattern etched in the form of vias, trenches, or both vias and trenches in the dielectric layer. The vias and/or trenches are then filled with metal in a deposition process to form the circuit pattern.
Spin coating of photoresist on wafers is carried out in an automated track system using wafer handling equipment which transport the wafers between the various photolithography operation stations, such as vapor prime resist spin coat, develop, baking and chilling stations. Robotic handling of the wafers minimizes particle generation and wafer damage. Automated wafer tracks enable various processing operations to be carried out simultaneously. Two types of automated track systems widely used in the industry are the TEL (Tokyo Electron Limited) track and the SVG (Silicon Valley Group) track.
Photoresist materials are coated onto the surface of a wafer by dispensing a photoresist fluid typically on the center of the wafer as the wafer rotates at high speeds within a stationary bowl or coater cup. The coater cup catches excess fluids and particles ejected from the rotating wafer during application of the photoresist. The photoresist fluid dispensed onto the center of the wafer is spread outwardly toward the edges of the wafer by surface tension generated by the centrifugal force of the rotating wafer. This facilitates uniform application of the liquid photoresist on the entire surface of the wafer.
In addition to photolithography, photoresist is often used as a sacrificial layer in etchback processes, such as copper etchback processes, in which topography created by surface features on the wafer is smoothed using an etching process. The sacrificial photoresist layer is deposited on the wafer and fills voids and low spots on the surface features. Dry etching of the photoresist layer is then carried out to smooth the surface features by removing high features at a faster rate than low features. The etching process is continued until the photoresist layer reaches a final thickness, with the photoresist material still filling the low-lying areas.
FIG. 1A illustrates a wafer 10 having deposited thereon a feature layer 12 having surface features (not shown) to be reduced in size in an etchback process. Accordingly, as the wafer 10 is rotated on a wafer support (not shown), liquid photoresist 14 is initially deposited from a photoresist dispenser 16 onto the feature layer 12 at the center of the wafer 10. The photoresist 14 will serve as a sacrificial layer during the subsequent etchback process.
As shown in FIG. 1B, the rotating motion of the wafer 10 causes centrifugal force to pull the photoresist 14 to the edge of the wafer 10. This causes the formation of an edge bead 17 which includes an annular edge bump 18, having an edge region 20, at the edge of the wafer 10 and layer 12.
As shown in FIG. 1C, prior to the etchback process, the edge region 20 of the edge bump 18 is removed in a one-step edge bead removal (EBR) process carried out at the end of the photoresist-coating step. The EBR process is typically performed by spraying a small quantity of solvent (not shown) on the underside of the wafer 10 as the wafer 10 is rotated. The solvent laps up over the edge of the wafer 10, thus dissolving and removing the edge region 20 from the edge bump 18. Accordingly, a reduced edge bump 18a, having a reduced height as compared to that of the edge bump 18, remains at the edge of the wafer 10 after the EBR step.
The wafer 10 is then subjected to the etchback process, in which dry etching is used to reduce the size of features fabricated in the feature layer 12. After the etchback process, as shown in FIG. 1D, a small quantity of photoresist 14 remains on the wafer 10 in the form of edge bump remnants 18b. These edge bump remnants 18b are a significant source of contaminant particles, which flake off and tend to contaminate active devices subsequently fabricated in and on the feature layer 12, thereby increasing defect densities of devices on the wafer 10. Accordingly, an edge bead removal method is needed for the complete removal of an edge bead from a wafer, particularly prior to an etchback process.
An object of the present invention is to provide a novel method which is capable of decreasing defect densities in devices fabricated on a wafer.
Another object of the present invention is to provide a novel multi-step edge bead removal (EBR) process for the substantially complete removal of an edge bead from a wafer.
Still another object of the present invention is to provide a multi-step EBR process which is effective in removing an edge bead from a wafer prior to an etchback or other process.
Yet another object of the present invention is to provide a novel EBR process which may include the removal of an edge bump portion from an edge bead, followed by the removal of an edge region from the edge bead, to prevent or at least minimize the formation of potential device-contaminating particles during a subsequent etchback process.